1. Technical Field
The present invention relates to an integrated circuit and a manufacturing method thereof, and more particularly, to an integrated circuit which can maximize an area of a capacitance capacitor without increasing a layout area. This may be done by forming a memory device in which a DRAM and a ferroelectric capacitor region are laminated.
2. Description of the Related Art
An integrated circuit is a basic device used in various electronic apparatuses, such as a computer system, a communication system, etc. Exemplary integrated circuits include a variety of circuits, such as a memory device, a digital signal processor (DSP), a system-on-chip (SoC), and a radio frequency identification (RFID) tag. In such integrated circuits, as many capacitors are designed to be included as chip layout allows.
For example, a ferroelectric random access memory (FeRAM) shows a data processing speed equivalent to that of a dynamic random access memory (DRAM), and preserves data even in a power off mode. Thus, FeRAM has been regarded as a next generation memory device. Moreover, FeRAM, which is a memory device almost identical in structure to DRAM, uses high remanent polarization which is a characteristic of a ferroelectric by employing the ferroelectric as a capacitor material. Even if an electric field is removed, data is not erased due to remanent polarization.
However, in a conventional RFID device, the RFID tag roughly consists of an analog block, a digital block, and a memory block. Such an RFID chip passive device must have a small layout area to minimize the production cost.
The conventional RFID device adopts a MOS capacitor or a polysilicon-insulator-polysilicon (PIP) or metal-insulator-metal (MIM) capacitor in fonnation of a capacitance capacitor of a pump circuit or another capacitance capacitor. In the case that the insulator is a paraelectric, a dielectric constant is reduced to relatively increase an area of the capacitor.
In addition, in a conventional integrated circuit such as a memory device, RFID device, SoC, or FeRAM, a peripheral circuit region and a capacitor region are disposed in separate regions on the same layer. That is, the MOS capacitor or the PIP or MIM capacitor has the same process level as that of the peripheral circuit region. Accordingly, in the conventional integrated circuit, the capacitor region and the peripheral circuit region cannot be formed in a lamination type to reduce the whole layout area.
For example, in an integrated circuit such as PRAM, MRAM, or flash, a memory cell does not include a capacitor. In the DRAM, a capacitor for a cell is used in a memory cell, and the MOS capacitor or the PIP or MIM capacitor is used in the peripheral circuit region. Since the circuit region using a complementary metal-oxide-semiconductor (CMOS) circuit and the capacitor are formed in the same process level, they cannot be formed in a lamination type.
In the conventional integrated circuit, the capacitor and the peripheral circuit region are disposed in different regions on the same layer. Therefore, the whole layout area is determined as the sum of the layout of the peripheral circuit region and the layout of the capacitor region. Thus, the whole layout area of the integrated circuit is increased.
On the other hand, as the capacitance of the DRAM increases, the operation voltage is decreased and power noise is increased. A capacitance of a capacitor required in a power pump for generating various internal voltages such as a pumping voltage VPP and a back bias voltage VBB is increased, and a capacitance of decoupling capacitors formed at an output terminal of the pump and a power terminal is increased. As a result, the area occupied by the decoupling capacitor and the capacitor associated with the pump is not reduced.